3.3v Ecl/pecl/hstl/lvds 2/4, 4/6 Clock Generation Chip

The MC100ES6039 is a low skew 2/4, 4/6 Clock generation chip designed explicitly for low skew Clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device CAN be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source CAN be AC coupled into the device. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal Clock is already in the LOW state. This avoids any chance of generating a runt Clock pulse on the internal Clock when the device is enabled/disabled as CAN happen with an asynchronous control. The internal enable Flip-Flop is clocked on the falling edge of the input Clock therefore, all associated specification limits are referenced to the negative edge of the Clock input. Upon startup, the internal Flip-Flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. By Freescale Semiconductor, Inc
MC100ES6039 's PackagesMC100ES6039 's pdf datasheet
MC100ES6039DW SO
MC100ES6039DWR2 SO
MC100ES6039EG SO
MC100ES6039EGR2 SO




MC100ES6039 Pinout, Pinouts
MC100ES6039 pinout,Pin out
This is one package pinout of MC100ES6039,If you need more pinouts please download MC100ES6039's pdf datasheet.

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