PECL/LVDS/HSTL-input PECL-output 2-GHz 2.5/ 3.3V 1:4 PECL Clock Driver With 2:1 Input Mux

PECL LVDs HSTL-input PECL-output 2-GHz 2.5/ 3.3V 1:4 PECL Clock Driver with 2:1 Input Mux MC100ES6130 The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout Buffer The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX which is ideal for redundant Clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed Logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt Clock pulse. By Integrated Device Technology
MC100ES6130 's PackagesMC100ES6130 's pdf datasheet

MC100ES6130 Pinout, Pinouts
MC100ES6130 pinout,Pin out
This is one package pinout of MC100ES6130,If you need more pinouts please download MC100ES6130's pdf datasheet.

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