5VECL 5-Bit 2:1 Mux-Latch

The MC10E154 MC100E154 contains five 2:1 multiplexers followed by transparent Latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A Logic HIGH on either LEN1 or LEN2 (or both) Latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. By ON Semiconductor
MC10E154 's PackagesMC10E154 's pdf datasheet
MC10E154FN PLCC
MC10E154FNG PLCC
MC10E154FNR2 PLCC
MC10E154FNR2G PLCC
MC100E154FN PLCC
MC100E154FNR2 PLCC
MC100E154




MC10E154 Pinout, Pinouts
MC10E154 pinout,Pin out
This is one package pinout of MC10E154,If you need more pinouts please download MC10E154's pdf datasheet.

MC10E154 Application circuits
MC10E154 circuits
This is one application circuit of MC10E154,If you need more circuits,please download MC10E154's pdf datasheet.


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