5VECL 6−Bit 2:1 Mux−Latch

The MC10E155 MC100E155 contains six 2:1 multiplexers followed by transparent Latches with singleended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A Logic HIGH on either LEN1 or LEN2 (or both) Latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. By ON Semiconductor
MC10E155 's PackagesMC10E155 's pdf datasheet
MC10E155FN PLCC
MC10E155FNG PLCC
MC10E155FNR2 PLCC
MC10E155FNR2G PLCC
MC100E155FN PLCC
MC100E155FNR2 PLCC
MC100E155




MC10E155 Pinout, Pinouts
MC10E155 pinout,Pin out
This is one package pinout of MC10E155,If you need more pinouts please download MC10E155's pdf datasheet.

MC10E155 Application circuits
MC10E155 circuits
This is one application circuit of MC10E155,If you need more circuits,please download MC10E155's pdf datasheet.


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