5VECL 3-Bit 4:1 Mux-Latch

The MC10E156 MC100E156 contains three 4:1 multiplexers followed by transparent Latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A Logic HIGH on either LEN1 or LEN2 (or both) Latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. By ON Semiconductor
MC10E156 's PackagesMC10E156 's pdf datasheet
MC10E156FN PLCC
MC10E156FNG PLCC
MC10E156FNR2 PLCC
MC10E156FNR2G PLCC
MC100E156FN
MC100E156




MC10E156 Pinout, Pinouts
MC10E156 pinout,Pin out
This is one package pinout of MC10E156,If you need more pinouts please download MC10E156's pdf datasheet.

MC10E156 Application circuits
MC10E156 circuits
This is one application circuit of MC10E156,If you need more circuits,please download MC10E156's pdf datasheet.


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