3-BIT 4:1 MUX-LATCH

The MC10E256 MC100E256 contains three 4:1 multiplexers followed by transparent Latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see Logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A Logic HIGH on LEN Latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. By ON Semiconductor
MC10E256 's PackagesMC10E256 's pdf datasheet



MC10E256 Pinout, Pinouts
MC10E256 pinout,Pin out
This is one package pinout of MC10E256,If you need more pinouts please download MC10E256's pdf datasheet.

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