3.3V / 5V ECL D Flip-Flop With Reset And Differential Clock

The MC10EP51 MC100EP51 is a differential Clock D flipflop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flipflop when the Clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the Clock The differential Clock inputs of the EP51 allow the device to be used as a negative edge triggered Flip-Flop By ON Semiconductor
MC10EP51 's PackagesMC10EP51 's pdf datasheet
MC10EP51D SOIC
MC10EP51DG SOIC
MC10EP51DR2 SOIC
MC10EP51DR2G SOIC
MC10EP51DT TSSOP
MC10EP51DTG TSSOP
MC10EP51DTR2 TSSOP
MC10EP51DTR2G TSSOP
MC10EP51MNR4G DFN
MC100EP51D SOIC
MC100EP51DG SOIC
MC100EP51DR2 SOIC
MC100EP51DR2G SOIC
MC100EP51DT TSSOP
MC100EP51DTG TSSOP
MC100EP51DTR2 TSSOP
MC100EP51DTR2G TSSOP
MC100EP51MNR4G DFN
MC100EP51




MC10EP51 Pinout, Pinouts
MC10EP51 pinout,Pin out
This is one package pinout of MC10EP51,If you need more pinouts please download MC10EP51's pdf datasheet.

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