Low Skew CMOS PLL Clock DriverThe MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew
outputs' frequency and phase onto an input reference Clock It is designed to provide Clock
distribution for high performance PC's and workstations.
The PLL allows the high current, low skew outputs to lock onto a single Clock input and
distribute it to multiple components on a board. The PLL also allows the MC88915 to
multiply a low frequency input Clock and distribute it locally at a higher (2X) system
frequency. Multiple 88915's CAN lock onto a single reference Clock which is ideal for
applications when a central system Clock must be distributed synchronously to multiple
boards (see Figure 9). By Integrated Device Technology
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