3.3 Volt Communications Clock VCXO PLL

The MK2049-34 is a Phase-Locked Loop (PLL) based Clock Synthesizer that accepts multiple input frequencies. With an 8 kHz Clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other Communications frequencies. This allows for the generation of Clocks frequency-locked and phase-locked to an 8 kHz Backplane Clock simplifying Clock synchronization in Communications systems. The MK2049-34 CAN also accept a T1 or E1 input Clock and provide the same output for loop Timing All outputs are frequency locked together and to the input. This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-34 is ideal for filtering jitter from 27 MHz Video Clocks or other Clocks with high jitter. Packaged in 20 pin SOIC 3.3 V 5% operation Fixed I/O phase relationship on all selections Meets the TR62411, ETS300-011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz Backplane Clock Loop Timing frequencies, or 10 to 36 MHz Locks to 8 kHz 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 to 36 MHz input and x1/x0.5 or x2/x4 outputs Exact internal ratios enable zero ppm error Output Clock rates include T1, E1, T3, E3, ISDN, xDSL, and OC3 submultiples Not recommended for new designs. Please use the MK2049-34A. By Integrated Device Technology
MK2049-34 's PackagesMK2049-34 's pdf datasheet
MK2049-34SAI SOIC
MK2049-34SAILF SOIC
MK2049-34SAILFTR SOIC
MK2049-34SAITR SOIC




MK2049-34 Pinout, Pinouts
MK2049-34 pinout,Pin out
This is one package pinout of MK2049-34,If you need more pinouts please download MK2049-34's pdf datasheet.

MK2049-34 Application circuits
MK2049-34 circuits
This is one application circuit of MK2049-34,If you need more circuits,please download MK2049-34's pdf datasheet.


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