3.3 Volt Communications Clock PLL

The MK2049-36 is a Phase-Locked Loop (PLL) based Clock Synthesizer that accepts multiple input frequencies. With an 8 kHz Clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet and other Communications frequencies. This allows for the generation of Clocks frequency-locked to an 8 kHz Backplane Clock simplifying Clock synchronization in Communications systems. This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-36 is ideal for filtering jitter from with high jitter Clocks Packaged in 20-pin SOIC Available in Pb (lead) free package 3.3 V 5% operation Meets the TR62411, ETS300-011, and GR-1244 specification for MTIE, Pull-in/Hold-inRange, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz Backplane Clock or 10 to 50 MHz Locks to 8 kHz 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 to 50 MHz input and x1/x0.5 or x1/x2 outputs Exact internal ratios enable zero ppm error Output Clock rates include T1, E1, T3, E3, and OC3 submultiples See also the MK2049-34 and the MK2049-45 By Integrated Device Technology
MK2049-36 's PackagesMK2049-36 's pdf datasheet
MK2049-36SI SOIC

MK2049-36 Pinout, Pinouts
MK2049-36 pinout,Pin out
This is one package pinout of MK2049-36,If you need more pinouts please download MK2049-36's pdf datasheet.

MK2049-36 Application circuits
MK2049-36 circuits
This is one application circuit of MK2049-36,If you need more circuits,please download MK2049-36's pdf datasheet.

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