3.3 Volt Communications Clock PLL

The MK2049-45A is a dual Phase-Locked Loop (PLL) device which CAN provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop Filter component selection. Buffer Mode accepts a 10 to 50 MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45A is ideal for filtering jitter from high frequency Clocks In External Mode, ICLK accepts an 8 kHz Clock and will produce output frequencies from a table of common communciations Clock rates, CLK and CLK/2. This allows for the generation of Clocks frequency-locked to an 8 kHz Backplane Clock simplifying Clock synchronization in Communications systems. The MK2049-45A CAN be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. Packaged in 20-pin SOIC 3.3 V + 5% operation Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz Backplane Clock or 10 to 50 MHz Locks to 8 kHz + 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs Exact internal ratios enable zero ppm error Output rates include T1, E1, T3, E3, and OC3 submultiples Available in Pb (lead) free package See also the MK2049-34 and MK2049-36 By Integrated Device Technology
MK2049-45 's PackagesMK2049-45 's pdf datasheet
MK2049-45SI SOIC

MK2049-45 Pinout, Pinouts
MK2049-45 pinout,Pin out
This is one package pinout of MK2049-45,If you need more pinouts please download MK2049-45's pdf datasheet.

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