VCXO-Based Clock Translator With High Multiplication

The MK2069-03 is a VCXO (Voltage Controlled Crystal Oscillator) based Clock Generator that offers system synchronization, jitter attenuation and frequency translation. It CAN accept an input Clock over a wide range of frequencies and produces a de-jittered, low phase noise Clock output. The device is optimized for user configuration by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop Filter components provide an additional level of performance tailoring. The MK2069-03 features a very wide range VCXO PLL feedback divider, allowing high frequency multiplication ratios and therefore the input of very low input reference frequencies. The lock detector (LD) output serves as a Clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input Clock while eliminating the generation of extra Clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low. Wide range VCXO PLL feedback divider allows high frequency multiplication ratios and the input of very low input reference frequencies Input Clock frequency of <1 kHz to 13.5 MHz Output Clock frequency of 500 kHz to 160 MHz PLL lock status output VCXO-based Clock generation offers very low jitter and phase noise generation, even with low frequency or jittery input Clock PLL Clear function (CLR input) allows the VCXO to free-run, offering a short term holdover function. 2nd PLL provides frequency translation of VCXO PLL to higher or alternate output frequencies. Device will free-run in the absence of an input Clock (or stopped input clock) based on the VCXO frequency pulled to minimum frequency limit. Low power CMOS technology 56-pin TSSOP package Single 3.3 V power supply By Integrated Device Technology
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MK2069-03 Pinout, Pinouts
MK2069-03 pinout,Pin out
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