Video Genlock PLL

The MK9173-01/-15 provide the Analog PLL circuit blocks to implement a Frequency Multiplier Because the device is configured to use an external divider in the PLL Clock feedback path, a large divider CAN be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input Clock to generate a high frequency output Clock The MK9173-01/-15 contains a phase detector, Charge Pump loop Filter and Voltage-Controlled Oscillator (VCO). The ICS674-01 CAN be used as the external feedback divider. A common application of the MK9173-01/-15 is the implementation of a Video genlock circuit. Because of this, the MK9173-01/-15 inputs operate on the negative-going Clock edge. The MK9173-01/-15 is pin and function compatible to the AV9173-01/15. The MK9173-01/15 is pin and function compatible to the AV9173-01/15. For new Video genlock designs, please refer to the ICS673-01, ICS1522 or ICS1523. Phase-detector VCO circuit block Ideal for genlock system Reference Clock range 12 kHz to 1 MHz for full output Clock range Output Clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See Allowable Input Frequency to Output Frequency table for conditions On-chip loop Filter Single 5 V power supply Low power CMOS technology 8-pin SOIC package For new Video genlock applications, please refer to the ICS673-01, ICS1522 or ICS1523. By Integrated Device Technology
MK9173 's PackagesMK9173 's pdf datasheet
MK9173-01CS08 SOIC
MK9173-01CS08LF SOIC
MK9173-01CS08T SOIC
MK9173-15CS08 SOIC
MK9173-15CS08LF SOIC
MK9173-15CS08T SOIC

MK9173 Pinout, Pinouts
MK9173 pinout,Pin out
This is one package pinout of MK9173,If you need more pinouts please download MK9173's pdf datasheet.

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