2, 4 Meg X 72 Nonbuffered Dram Dimms Technology

The MT9LD272A(X) and MT18LD472A X) are randomly accessed 16MB and 32MB Memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 21/22 address bits, which are en- tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0- A10) at CAS# time. READ and WRITE cycles are selected with the WE# input. A Logic HIGH on WE# dictates read mode, while a Logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY- WRITE cycles, OE# must be taken HIGH to disable the data- outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location. By Micron Semiconductor Products
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MT18LD472A Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
MT18LD472A circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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