The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configu- ration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time. RAS is used to latch the first 11 bits and CAS the latter 11 bits. A READ or WRITE cycle is selected with the WE input. A Logic HIGH on WE dictates READ mode while a Logic LOW on WE dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the By Austin Semiconductor, Inc.
MT4C1004J 's PackagesMT4C1004J 's pdf datasheet

MT4C1004J Pinout, Pinouts
MT4C1004J pinout,Pin out
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