1 MEG X 4 DRAM Fast Page Mode DRAM

The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the first 10 bits and CAS the later 10 bits. A READ or WRITE By Austin Semiconductor, Inc.
MT4C4001J 's PackagesMT4C4001J 's pdf datasheet
MT4C4001JCZ-8-883C
5962-9084703MNA
MT4C4001JC-8-883C
5962-9084703MUA
MT4C4001JCZ-10-883C
5962-9084702MNA
MT4C4001JC-10-883C
5962-9084702MUA
MT4C4001JCZ-12-883C
5962-9084701MNA
MT4C4001JC-12-883C
5962-9084701MUA
MT4C4001JCN-8-883C
5962-9084703MRA
MT4C4001JECN-8-883C
5962-9084703MTA
MT4C4001JCN-10-883C
5962-9084702MRA
MT4C4001JECN-10-883C
5962-9084702MTA
MT4C4001JCN-12-883C
5962-9084701MRA
MT4C4001JECN-12-883C
5962-9084701MTA




MT4C4001J Pinout, Pinouts
MT4C4001J pinout,Pin out
This is one package pinout of MT4C4001J,If you need more pinouts please download MT4C4001J's pdf datasheet.

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MT4C4001J Application Notes MT4C4001J RoHS MT4C4001J Circuits MT4C4001J footprint
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