1 MEG X 4 DRAM Fast Page Mode DRAMThe MT4C4001J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS is used to latch the
first 10 bits and CAS the later 10 bits. A READ or WRITE By Austin Semiconductor, Inc.
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| MT4C4001J Pb-Free | MT4C4001J Cross Reference | MT4C4001J Schematic | MT4C4001J Distributor |
| MT4C4001J Application Notes | MT4C4001J RoHS | MT4C4001J Circuits | MT4C4001J footprint |
