T1/e1 System Synchronizer

The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides Timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9043 generates ST-BUS Clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9043 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced, and Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range, phase change slope, and MTIE requirements for these specifications. By Zarlink Semiconductor
MT9043 's PackagesMT9043 's pdf datasheet
MT9043AN




MT9043 Pinout, Pinouts
MT9043 pinout,Pin out
This is one package pinout of MT9043,If you need more pinouts please download MT9043's pdf datasheet.

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