128m [x8/x16] Single 3v Page Mode Mtp Memory

The MXIC's MX26L12811MC series MTP use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density MTP memory solution with reliable performance and most cost-effective. The device organized as by 8 bits or by 16 bits of output bus. The device is packaged in 44-Lead SOP. It is de- signed to be reprogrammed and erased in system or in standard EPROM programmers. The device offers fast access time and allowing opera- tion of high-speed Microprocessors without wait states. The device augment EPROM functionality with in-circuit electrical erasure and programming. The device uses a command Register to manage this functionality. The MXIC's Nbit technology reliably stores memory con- tents even after the specific erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's charac- ter to trap or release charges from ONO layer. The device uses a 3.0V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algo- rithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V By Unkown
MX26L12811MC 's PackagesMX26L12811MC 's pdf datasheet

MX26L12811MC Pinout, Pinouts
MX26L12811MC pinout,Pin out
This is one package pinout of MX26L12811MC,If you need more pinouts please download MX26L12811MC's pdf datasheet.

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