Mpc5534 Microcontroller Reference Manual

 The MPC5534 Microcontroller (MCU) is a member of the MPC5500 family of next generation powertrain
microcontrollers built on Power Architecture™ technology. The MPC5500 family contains a host
processor core that complies with the Power Architecture embedded category, which is 100 percent user
mode compatible with the original Power PC™ user instruction set architecture (UISA). This family of
parts contains many new features coupled with high-performance CMOS technology to provide significant
performance improvement over the MPC565.
The e200z3 CPU of the MPC5500 family is part of the family of CPU cores that implement versions built
on the Power Architecture embedded category. This core also has additional instructions, including digital
signal processing (DSP) instructions, beyond the classic PowerPC instruction set.
The e200z3 of the MPC5534 is compatible with the PowerPC Book E architecture. It is 100% user mode
compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture
has enhancements that improve the PowerPC architecture’s fit in embedded applications. This core also
has additional instructions, including digital signal processing (DSP) instructions, beyond the classic
PowerPC instruction set. MPC5533 MPC5534 MPC5553 MPC5554
The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to achieve significant code size footprint reduction.
 The MPC5534 MCU has an on-chip 40-channel Enhanced Queued Dual Analog-to-digital Converter
(eQADC), with 5 V conversion range.
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