DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

The HC112 devices SN54HC112, SN74HC112 contain two independent J-K negative-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the Clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops perform as toggle Flip-Flops by tying J and K high. The SN54HC112 is characterized for operation over the full military temperature range of 55C to 125C. The SN74HC112 is characterized for operation from 40C to 85C. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN54HC112FK Rochester Electronics LLC J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, CQCC20, CERAMIC, CC-20
SN54HC112J Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
N54HC112 's PackagesN54HC112 's pdf datasheet



N54HC112 Pinout, Pinouts
N54HC112 pinout,Pin out
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