2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip−Flop With Reset

The NB4L52 is a differential Data and Clock D flipflop with a differential asynchronous Reset. The differential inputs incorporate internal 50  termination resistors and will accept PECL, LVPECL, LVCMOS, LVTTL, CML, or LVDs Logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3x3 mm 16 pin QFN package. By ON Semiconductor
NB4L52 's PackagesNB4L52 's pdf datasheet

NB4L52 Pinout, Pinouts
NB4L52 pinout,Pin out
This is one package pinout of NB4L52,If you need more pinouts please download NB4L52's pdf datasheet.

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