4K-Bit Standard 2-Wire Bus Interface Serial EEPROMThe NM24C04 NM24C05 devices are 4096 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 2Kbit) of the memory of the NM24C05 CAN be
write protected by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.
This Communications protocol uses Clock (SCL) and DATA
I/O (SDA) lines to synchronously Clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.) By Fairchild Semiconductor
|
|
NM24C04 Pb-Free | NM24C04 Cross Reference | NM24C04 Schematic | NM24C04 Distributor |
NM24C04 Application Notes | NM24C04 RoHS | NM24C04 Circuits | NM24C04 footprint |