64K-Bit Extended 2-Wire Bus Interface Serial EEPROM With Write Protect

The NM24C65 devices are 65,536 bits of CMOS nonvolatile electrically erasable memory. These devices offer the designer different low voltage and low power options, and they conform to all in the Extended IIC 2-wire protocol. Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements. The upper half of the memory CAN be disabled (Write Protection) by connecting the WP pin to VCC. This section of memory then becomes ROM. This Communication protocol uses Clock (SCL) and DATA I/O (SDA) lines to synchronously Clock data between the master (for example a microprocessor) and the slave EEPROM device(s). By Fairchild Semiconductor
NM24C65 's PackagesNM24C65 's pdf datasheet

NM24C65 Pinout, Pinouts
NM24C65 pinout,Pin out
This is one package pinout of NM24C65,If you need more pinouts please download NM24C65's pdf datasheet.

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