512Mb DDR2 SDRAM B-Die

The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high- speed CMOS Double Data Rate 2 SDRAM containing 536,870,912 bits. It is internally configured as a quad-bank DRAM The 512Mb chip is organized as either 32Mbit x 4 I/O x 4 bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. These synchronous devices achieve high speed dou- ble-data-rate transfer rates of up to 533 Mb/sec/pin for gen- eral applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data- output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential Clocks Inputs are latched at the cross point of differential Clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fash- ion. A 14 bit address bus for x4 and x8 organised compo- nents and a 13 bit address bus for x16 components is used to convey row, column, and bank address devices. These devices operate with a single 1.8V+/-0.1V power sup- ply and are available in BGA packages. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. By Nanya Techology
NT5TU128M4BE 's PackagesNT5TU128M4BE 's pdf datasheet
NT5TU128M4BE-5A BGA
NT5TU128M4BE-37B BGA
NT5TU128M4BE-3C BGA
NT5TU128M4BE-25C BGA
NT5TU128M4BE-25D BGA
NT5TU64M8BE-5A BGA
NT5TU64M8BE-37B BGA
NT5TU64M8BE-3C BGA
NT5TU64M8BE-25C BGA
NT5TU64M8BE-25D BGA
NT5TU32M16BG-5A BGA
NT5TU32M16BG-37B BGA
NT5TU32M16BG-3C BGA
NT5TU32M16BG-25D BGA




NT5TU128M4BE Pinout, Pinouts
NT5TU128M4BE pinout,Pin out
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