NT5TU512T4BU-37B

The 2Gb Stacked Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing 2,147,483,648 bits. It is internally configured as a octal-bank DRAM The 2Gb chip is organized as either 64Mbit x 4 I/O x 8 bank, 32Mbit x 8 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data- output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential Clocks Inputs are latched at the cross point of differential Clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fash- ion. A 14 bit address bus organised components is used to convey row, column, and bank address devices. By Nanya Techology
NT5TU512T4BU-37B 's PackagesNT5TU512T4BU-37B 's pdf datasheet
NT5TU512T4BU-3C
NT5TU512T4BU-25D
NT5TU256T8BU-37B
NT5TU256T8BU-3C
NT5TU256T8BU-25D




NT5TU512T4BU-37B Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
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