74ABT899 9-bit Dual Latch Transceiver With 8-bit Parity Generator/checker (3-State)

The 74ABT899 is a 9-bit to 9-bit parity transceiver with separate transparent Latches for the A bus and B bus. Either bus CAN generate or check parity. The parity bit CAN be fed-through with no change or the generated parity CAN be substituted with the SEL input. Parity error checking of the A and B bus Latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT899 features independent latch enables for the A and B bus Latches a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
By NXP Semiconductors
Part Manufacturer Description Datasheet Samples
SN74ABT8996PWLE Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers 24-TSSOP -40 to 85
SN74ABT8996PWR Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers 24-TSSOP -40 to 85
SN74ABT8996DW Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers 24-SOIC -40 to 85
SN74ABT8996DWR Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers 24-SOIC -40 to 85
SN74ABT8996PW Texas Instruments 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers 24-TSSOP -40 to 85
74ABT899 's Packages74ABT899 's pdf datasheet
74ABT899A
74ABT899D SO
74ABT899DB SSOP




74ABT899 Pinout, Pinouts
74ABT899 pinout,Pin out
This is one package pinout of 74ABT899,If you need more pinouts please download 74ABT899's pdf datasheet.

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