PC Card And Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer

The Texas Instruments PCI4510R device is an integrated single-socket PC Card controller with an IEEE 1394 open host controller link-layer controller (LLC) and two-port 1394 PHY This high performance integrated solution provides the latest in both PC Card and IEEE 1394 technology. The controller is compliant with PCI Local Bus Specification. Function 0 provides the independent PC Card socket controller compliant with the latest PC Card Standards. The controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required. There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI4510R controller. The PCI4510R controller is Register compatible with the Intel 82365SL-DF ExCA controller and implements the host Interface defined in the PC Card Standard. The internal data path Logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with sustained bursting. The controller CAN be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering. Function 1 of the controller is an integrated IEEE 1394a-2000 open host controller Interface (OHCI) PHY link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The controller provides two 1394 ports that have separate cable bias (TPBIAS). The controller also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal control Registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and it provides plug-and-play (PnP) compatibility. Furthermore, the controller is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The controller supports the D0, D1, D2, and D3 power states. The controller provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the Memory controller Because PCI latency CAN be large, deep FIFOs are provided to Buffer the IEEE 1394 data. The controller provides physical write posting Buffers and a highly-tuned physical data path for SBP-2 performance. The controller also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding Buffers
The PHY-layer provides the digital and Analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external Clock may be provided instead of a crystal. An internal Oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the Clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz Clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally in synchronization with the 49.152-MHz system Clock These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair(s). Various implementation-specific functions and general-purpose inputs and outputs are provided through several multifunction terminals. These terminals present a system with options, such as PCI LOCK and parallel IRQs. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming Interface is included for the general-purpose inputs and outputs. The controller is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption. The controller also has a four-pin Interface compatible with both the TI TPS2211A and TPS2221 Power Switches An advanced CMOS process achieves low power consumption and allows the controller to operate at PCI Clock rates up to 33 MHz.
By Texas Instruments
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