PCK2057 70-190 MHz I2C Differential 1:10 Clock Driver

The PCK2057 is a high-performance, low-skew, low-jitter zero delay Buffer that distributes a differential Clock input pair (CLK, CLK) to ten differential pairs of Clock outputs and one differential pair of feedback Clock outputs. The Clock outputs are controlled by the Clock inputs (CLK, CLK), the feedback Clocks (FBIN, FBIN), the 2-line serial Interface (SDA, SCL), and the Analog power input (AV DD ). The two-line serial Interface (I C) CAN put the individual output Clock pairs in a high-impedance state. When AV DD is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 kbits) I C Interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 kW). Two 8-bit, 2-line serial Registers provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair CAN be placed in a high-impedance mode, when a low-level control bit is written to the control Register The Registers must be accessed in sequential order (i.e., random access of the Registers is not supported). The IC Interface circuit CAN be supplied with either 2.5 V or 3.3 V (V DD I C). Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL This stabilization time is required following power-up.
By NXP Semiconductors
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PCK2057 Pinout, Pinouts
PCK2057 pinout,Pin out
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