3.3V, Low-Noise Phase-Locked Loop Clock Driver With 9 Clock Outputs

The PI6C2509-133 is a quiet, low-skew, low-jitter, phase-lock loop (PLL) Clock Driver distributing low-noise Clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any Clock output will be nearly zero. This zero-delay feature allows the CLK_IN input Clock to be distributed, providing 5 Clocks for the first bank, and an additional 4 Clocks for the second bank. By Pericom Semiconductor Corporation
PI6C2509-133 's PackagesPI6C2509-133 's pdf datasheet



PI6C2509-133 Pinout, Pinouts
PI6C2509-133 pinout,Pin out
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