2.5V, 200MHz PLL Clock Driver

The PI6CV847 PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay Buffer that distributes a differential Clock input pair (CLK, CLK) to five differential pairs of Clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback Clock outputs (FBOUT, FBOUT). The Clock outputs are controlled by the input Clocks (CLK, CLK), the feedback Clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The PI6CV847 is able to track Spread Spectrum Clocking to reduce EMI By Pericom Semiconductor Corporation
PI6CV847 's PackagesPI6CV847 's pdf datasheet
PI6CV847L
PI6CV847LE




PI6CV847 Pinout, Pinouts
PI6CV847 pinout,Pin out
This is one package pinout of PI6CV847,If you need more pinouts please download PI6CV847's pdf datasheet.

PI6CV847 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

PI6CV847 Pb-Free PI6CV847 Cross Reference PI6CV847 Schematic PI6CV847 Distributor
PI6CV847 Application Notes PI6CV847 RoHS PI6CV847 Circuits PI6CV847 footprint