2.5V, 170 MHz, 5 Output SSTL-2 Zero Delay Clock Driver

PI6CV855 PLL Clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay Buffer that distributes a differential Clock input pair (CLK, CLK) to five differential pairs of Clock outputs (Y[0:4], Y[0:4]) and one differential pair feedback Clock outputs (FBOUT, FBOUT). The Clock outputs are controlled by the input Clocks (CLK, CLK), the feedback Clocks (FBIN,FBIN), and the Analog Power input (AVDD). When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The PI6CV855 is able to track Spread Spectrum Clocking to reduce EMI By Pericom Semiconductor Corporation
PI6CV855 's PackagesPI6CV855 's pdf datasheet

PI6CV855 Pinout, Pinouts
PI6CV855 pinout,Pin out
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