2.5V, 170 MHz, 10 Output SSTL-2 Zero Delay Clock Driver, High Drive For Stacked DDR DIMMPI6CV857 PLL Clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V
AVDD operation and differential data input and output levels.
Package options include plastic Thin Shrink Small-Outline Package
(TSSOP).The device is a zero delay Buffer that distributes a differ-
ential Clock input pair (CLK, CLK) to ten differential pairs of Clock
outputs (Y[0:9], Y[0:9]) and one differential pair feedback Clock
outputs (FBOUT,FBOUT) . The Clock outputs are controlled by the
input Clocks (CLK, CLK), the feedback Clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AVDD).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential Clock
outputs are 3-stated. When the AVDD is strapped low, the PLL is
turned off and bypassed for test purposes. By Pericom Semiconductor Corporation
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PI6CV857 Pb-Free | PI6CV857 Cross Reference | PI6CV857 Schematic | PI6CV857 Distributor |
PI6CV857 Application Notes | PI6CV857 RoHS | PI6CV857 Circuits | PI6CV857 footprint |