2.5V/2.6V, 220 MHz, 10 Output SSTL-2 Clock Driver For DDR DIMM

PI6CVF857 PLL Clock device is developed for registered DDR DIMM applications. The device is a zero-delay Buffer that distributes a differential Clock input pair (CLK, CLK) to ten differential pairs of Clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback Clock outputs (FBOUT,FBOUT) . The Clock outputs are controlled by the input Clocks (CLK, CLK), the feedback Clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN), and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off, and the differential Clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. By Pericom Semiconductor Corporation
PI6CVF857 's PackagesPI6CVF857 's pdf datasheet
PI6CVF857A
PI6CVF857AE
PI6CVF857ZDE




PI6CVF857 Pinout, Pinouts
PI6CVF857 pinout,Pin out
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