1:6 Differential Clock Distribution Chip Semiconductor Corporation

The PI90LV211 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320 MHz with low skew. The PI90LV211 is a low skew 1:6 fanout device designed explicitly for low skew Clock Distribution applications. The device features a multi- plexed Clock input to allow for the distribution of a lower speed scan or test Clock with the high-speed system Clock When LOW the SEL pin will select the differential Clock input. Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative transition of the CLK (or SCLK) input. The enable function is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt Clock pulse when the device is enabled/disabled as CAN happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input Clock therefore all associated specification limits are referenced to the negative edge of the Clock input. Individual synchronous enable controls and multiplexed Clock in- puts make this device ideal as the first level distribution unit in a distribution tree. The individual enables could be used to allow for the disabling of individual cards on a Backplane in fault tolerant designs. By Pericom Semiconductor Corporation
PI90LV211 's PackagesPI90LV211 's pdf datasheet

PI90LV211 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
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