Low Skew Output Buffer

The PL102-10 is a high performance, low skew, low j itter zero delay Buffer designed to distribute high speed Clocks and is avai lable in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the input. The synchronization is establ ished via CLKOUT feed back to the input of the PLL Since the skew between the input and output is less than 350 ps, the device acts as a zero delay Buffer By PhaseLink Corp.
Part Manufacturer Description Datasheet Samples
BQ76PL102RGTT Texas Instruments PowerLAN Dual-Cell Li-Ion Battery Monitor with PowerPump Cell Balancing 16-VQFN -40 to 85
BQ76PL102RGTR Texas Instruments PowerLAN Dual-Cell Li-Ion Battery Monitor with PowerPump Cell Balancing 16-VQFN -40 to 85
PL102-10 's PackagesPL102-10 's pdf datasheet
PL102-10SC
PL102-10SC-R
PL102-10TC-R




PL102-10 Pinout, Pinouts
PL102-10 pinout,Pin out
This is one package pinout of PL102-10,If you need more pinouts please download PL102-10's pdf datasheet.

PL102-10 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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