3.3V Zero Delay Buffer

The PL123-08 is a PLL-based zero-delay Buffer family, used to distribute up to eight outputs. Select inputs S2 and S1 control the state of the two output banks. An external feedback pin enables removing delay from external components. It also provides adjustable input- to-output delay by varying its loading relative to the output pin loading. By PhaseLink Corp.
PL123-08 's PackagesPL123-08 's pdf datasheet
PL123-08HOC
P123-08H
PL123-08HOC-R
PL123-08SC
P123-08
PL123-08SC-R
PL123-08HSC
PL123-08HSC-R
PL123-082SC
P123-082
PL123-082SC-R
PL123-083SC
P123-083
PL123-083SC-R
PL123-08HOI
PL123-08HOI-R
PL123-08SI
PL123-08SI-R
PL123-08HSI
PL123-08HSI-R
PL123-082SI
PL123-082SI-R
PL123-083SI
PL123-083SI-R
PL123-08HOCA
PL123-08HOCA-R
PL123-08SCA
PL123-08SCA-R
PL123-08HSCA
PL123-08HSCA-R
PL123-082SCA
PL123-082SCA-R
PL123-083SCA
PL123-083SCA-R
PL123-08HOIA
PL123-08HOIA-R
PL123-08SIA
PL123-08SIA-R
PL123-08HSIA
PL123-08HSIA-R
PL123-082SIA
PL123-082SIA-R
PL123-083SIA
PL123-083SIA-R




PL123-08 Pinout, Pinouts
PL123-08 pinout,Pin out
This is one package pinout of PL123-08,If you need more pinouts please download PL123-08's pdf datasheet.

PL123-08 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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PL123-08 Pb-Free PL123-08 Cross Reference PL123-08 Schematic PL123-08 Distributor
PL123-08 Application Notes PL123-08 RoHS PL123-08 Circuits PL123-08 footprint