Low Skew Output Buffer

The PLL102-03 is a high performance, low skew, low jitter zero delay Buffer designed to distribute high speed Clocks and is available in an 8-pin SOIC pack- age. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL Since the skew be- tween the input and output is less than 350 ps, the device acts as a zero delay Buffer By PhaseLink Corp.
PLL102-03 's PackagesPLL102-03 's pdf datasheet
PLL102-03SC SOIC
P102-03SC SOIC
PLL102-03SC-R SOIC
PLL102-03SCL SOIC
P102-03SCL SOIC
PLL102-03SCL-R SOIC




PLL102-03 Pinout, Pinouts
PLL102-03 pinout,Pin out
This is one package pinout of PLL102-03,If you need more pinouts please download PLL102-03's pdf datasheet.

PLL102-03 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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