Low Skew Output Buffer

The PLL102-05 is a high performance, low skew, low jitter zero delay Buffer designed to distribute high speed Clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL Since the skew between the input and output is less than 350 ps, the device acts as a zero delay Buffer By PhaseLink Corp.
PLL102-05 's PackagesPLL102-05 's pdf datasheet
PLL102-05SC-R SOIC
P102-05SC SOIC
PLL102-05SC SOIC
PLL102-05SCL-R SOIC
P102-05SCL SOIC
PLL102-05SCL SOIC




PLL102-05 Pinout, Pinouts
PLL102-05 pinout,Pin out
This is one package pinout of PLL102-05,If you need more pinouts please download PLL102-05's pdf datasheet.

PLL102-05 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

PLL102-05 Pb-Free PLL102-05 Cross Reference PLL102-05 Schematic PLL102-05 Distributor
PLL102-05 Application Notes PLL102-05 RoHS PLL102-05 Circuits PLL102-05 footprint