Low Skew Output BufferThe PLL102-05 is a high performance, low skew, low
jitter zero delay Buffer designed to distribute high
speed Clocks and is available in 8-pin SOIC package. It
has four outputs that are synchronized with the input.
The synchronization is established via CLKOUT feed
back to the input of the PLL Since the skew between
the input and output is less than 350 ps, the device
acts as a zero delay Buffer By PhaseLink Corp.
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PLL102-05 Pb-Free | PLL102-05 Cross Reference | PLL102-05 Schematic | PLL102-05 Distributor |
PLL102-05 Application Notes | PLL102-05 RoHS | PLL102-05 Circuits | PLL102-05 footprint |