Low Skew Output Buffer - Phaselink Corporation

The PLL102-15 is a high performance, low skew, low jitter zero delay Buffer designed to di stribute high speed Clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of the PLL Since the skew b etween the input and output is less than 350 ps, the device acts as a zero delay Buffer By PhaseLink Corp.
PLL102-15 's PackagesPLL102-15 's pdf datasheet



PLL102-15 Pinout, Pinouts
PLL102-15 pinout,Pin out
This is one package pinout of PLL102-15,If you need more pinouts please download PLL102-15's pdf datasheet.

PLL102-15 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

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