Ddr Sdram Buffer With 5 Ddr Or 3 Sdr/3 Ddr Dimms - Phaselink Corporation

The PLL103-53 is designed as a 3.3V/2.5V Buffer to distribute high-speed Clocks in PC applications. The device has 30 outputs. These outputs CAN be configured to support 4 unbuffered DDR (Double Data Rate) DIMMS or to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-53 CAN be used in conjunction with the PLL202-14/-54 or similar Clock Synthesizer for the VIA Pro 266 chipset. The PLL103-53 also has an I2C Interface which CAN enable or disable each output Clock When power up, all output Clocks are enabled (has internal pull up). By PhaseLink Corp.
PLL103-53 's PackagesPLL103-53 's pdf datasheet

PLL103-53 Pinout, Pinouts
PLL103-53 pinout,Pin out
This is one package pinout of PLL103-53,If you need more pinouts please download PLL103-53's pdf datasheet.

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