High Speed Translator Buffers: Single Ended To PECL Or LVDS

The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator Buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential out- puts (PECL for PLL130-68 or LVDs for PLL130- 69). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing CAN be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDs or PECL. By PhaseLink Corp.
PLL130-68 's PackagesPLL130-68 's pdf datasheet
P130-68 QFN
P130-69 QFN

PLL130-68 Pinout, Pinouts
PLL130-68 pinout,Pin out
This is one package pinout of PLL130-68,If you need more pinouts please download PLL130-68's pdf datasheet.

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