64 Macrocell Cpld - Nxp Semiconductors

The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD With the FZP design technique, the PZ3064 offers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than 50A at standby without the need for turbo bits or other power down schemes. By replacing conventional sense Amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS Gates the dynamic power is also substantially lower than any competing CPLD 70% lower at 50MHz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Philips also offers the high speed PZ5064 CPLD that offers these features in a full 5V implementation. The Philips FZP CPLDs introduce the new patent-pending XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible Logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each Logic block provides a fast 10ns PAL path with 5 dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that CAN allocate the PLA product terms to any output in the Logic block. This combination allows Logic to be allocated efficiently throughout the Logic block and supports as many as 37 product terms on an output. The speed with which Logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case tPDs of only 12.5ns from any pin to any other pin. In addition, Logic that is common to multiple outputs CAN be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. By NXP Semiconductors
PZ3064 's PackagesPZ3064 's pdf datasheet
PZ3064-10A44
PZ3064-12A44
PZ3064I12A44
PZ3064I15A44
PZ3064-10BC
PZ3064-12BC
PZ3064I12BC
PZ3064I15BC
PZ3064-10A68
PZ3064-12A68
PZ3064I12A68
PZ3064I15A68
PZ3064-10A84
PZ3064-12A84
PZ3064I12A84
PZ3064I15A84
PZ3064-10BB1
PZ3064-12BB1
PZ3064I12BB1
PZ3064I15BB1




PZ3064 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
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