Low Skew Cmos Pll Clock Driver With Integrated Loop Filter

The QS5930T Clock Driver uses an internal Phase locked loop (PLL) to lock low skew outputs to a reference Clock input. Six outputs are available: Q0Q4, Q/2. Careful layout and design ensure < 250ps skew between the Q0Q4, and Q/2 outputs. The QS5930T includes an internal RC Filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL CAN also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5930T is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe sys- tems. Several CAN be used in parallel or scattered throughout a sys- tem for guaranteed low skew, system-wide Clock Distribution networks. In the QSOP package, the QS5930T Clock Driver represents the best value in small form factor, high-performance Clock management prod- ucts. By Integrated Device Technology
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QS5930T Pinout, Pinouts
QS5930T pinout,Pin out
This is one package pinout of QS5930T,If you need more pinouts please download QS5930T's pdf datasheet.

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