3.3v Low Skew Cmos Pll Clock Driver With Integrated Loop Filter - Integrated Device Technology

The QS5LV919 Clock Driver uses an internal Phase locked loop (PLL) to lock low skew outputs to one of two reference Clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs. The QS5LV919 includes an internal RC Filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL CAN also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multi- board computers, networking hardware, and mainframe systems. Sev- eral CAN be used in parallel or scattered throughout a system for guar- anteed low skew, system-wide Clock Distribution networks. For more information on PLL Clock Driver products, see Application Note AN-227. By Integrated Device Technology
QS5LV919 's PackagesQS5LV919 's pdf datasheet



QS5LV919 Pinout, Pinouts
QS5LV919 pinout,Pin out
This is one package pinout of QS5LV919,If you need more pinouts please download QS5LV919's pdf datasheet.

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