3.3v Low Skew Cmos Pll Clock Driver With Integrated Loop Filter - Integrated Device Technology

The QS5LV931 Clock Driver uses an internal Phase locked loop (PLL) to lock low skew outputs to a reference Clock input. Six outputs are available: Q0Q4, Q/2. Careful layout and design ensure <300ps skew between the Q0Q4, and Q/2 outputs. The QS5LV931 includes an internal RC Filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL CAN also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5LV931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several CAN be used in parallel or scattered throughout a system for guaranteed low skew, system-wide Clock Distribution networks. In the QSOP package, the QS5LV931 Clock Driver represents the best value in small form factor, high-performance Clock management products. For more information on PLL Clock Driver products, see Application Note AN-227. By Integrated Device Technology