This Manual Describes SAMSUNG\'s S3C2410A 16/32-bit RISC Microprocessor

This manual describes SAMSUNG's S3C2410A 16/32-bit RISC Microprocessor This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro- controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select Logic and SDRAM Controller), 3- ch UART 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC 8-ch 10-bit ADC and Touch Screen Interface IIC- BUS Interface IIS-BUS Interface USB Host, USB Device, SD Host & Multi-Media Card Interface 2-ch SPI and PLL for Clock generation. The S3C2410A was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA). The S3C2410A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By Samsung Semiconductor, Inc.
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