SAA7214 Transport MPEG2 Source Decoder

SAA7214 system overview The device is part of a comprehensive source decoding kit which contains all the hardware and software required to receive and decode MPEG2 transport streams, including descrambling, demultiplexing. In addition, it includes a MIPS PR3001 RISC CPU core and several peripheral Interfaces such as UARTs IC-bus units, and an IEEE 1284 (Centronics) Interface The SAA7214 is therefore capable of performing all controller tasks in digital Television applications such as set-top boxes. The SAA7214 is compliant to DVB specification. The SAA7214 receives transport streams through a versatile stream input Interface capable of handling both byte-parallel and bit-serial streams, in various formats, supporting data streams up to and including 13.5 Mbytes/s (108 Mbits/s). The stream data is first applied to an on-chip descrambler incorporating DVB descrambling algorithm, on the basis of 6 control word pairs stored in on-chip RAM. Demultiplexing is subsequently applied to the stream, to separate up to 32 individual data streams. The demultiplexer section includes Clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3001 CPU core. To support advanced board testing facilities, the SAA7214 includes boundary scan test hardware, in accordance with the JTAG standard. The device features a low-power sleep mode, which is capable of sustaining set-top box standby functionality, thus eliminating the need for a separate front-panel controller. The SAA7214 requires a supply voltage of 3.3 V and some devices input and output Interfaces are 5 V tolerant. The device is mounted in a SQFP208 package.
By NXP Semiconductors
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