Synchronous Clock Generator

The SCG2500A is a Mixed-Signal phase lock loop generating CMOS outputs from an intrinsically low jitter Voltage Controlled Crystal Oscillator The SCG2500A is based on Connor-Winfield’s SCG2500 series product line. The SCG2500A CAN lock to one of two possible reference inputs at 8 kHz that are selectable using one input select pin. The SCG2500A has an improved Filter compared to the SCG2500. The new Filter allows the SCG2500A to more closely track the selected input reference and lowers switching MTIEs. The SCG2500A provides 3 alarm outputs, Loss of Reference A, (LOR A) Loss of Reference B, (LOR B), and Loss of Lock, (LOL) as compared to the SCG2500’s combined alarms. In the event of a LOL condition, the LOL alarm will activate in 1us of the next rising edge of the internal, 8 kHz reference. Switching references within 100 ns will then comply with GR-253-CORE requirements. LOR A and LOR B independently monitor the input references. If Both references are lost the unit will go into Free Run automatically. When both references are lost, the unit should be forced into Free Run (pin 5 = 1). LOR A and LOR B CAN then be monitored until the references return. Refer to Table 6 for more operational details. The reference output at 8 kHz is derived from the Oscillator output. Note that the offset between the filtered output and the reference input will change with each reference rearrangement. By Connor-Winfield VCXOs
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