The SI5316 is a low jitter, precision jitter Attenuator for high-speed Communication systems, including OC-48, OC-192, 10G Ethernet and 10G Fibre Channel. The SI5316 accepts dual Clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated Clock output at the same frequency. Within each of these Clock ranges, the device CAN be tuned approximately 15% higher than nominal SONET SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The SI5316 is based on Silicon Laboratories' 3rd-generation DSPLL technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop Filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the SI5316 is ideal for providing jitter attenuation in high performance Timing applications. By Silicon Laboratories
SI5316 's PackagesSI5316 's pdf datasheet

SI5316 Pinout, Pinouts
SI5316 pinout,Pin out
This is one package pinout of SI5316,If you need more pinouts please download SI5316's pdf datasheet.

SI5316 Application circuits
SI5316 circuits
This is one application circuit of SI5316,If you need more circuits,please download SI5316's pdf datasheet.

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