The SI5368 is a jitter-attenuating precision Clock multiplier for applications requiring sub 1 ps rms jitter performance. The SI5368 accepts four Clock inputs ranging from 2 kHz to 710 MHz and generates five Clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The SI5368 input Clock frequency and Clock multiplication ratio are programmable through an I 2C or SPI Interface The SI5368 is based on Silicon Laboratories' 3rd-generation DSPLL technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop Filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the SI5368 is ideal for providing Clock multiplication and jitter attenuation in high performance Timing applications. By Silicon Laboratories
SI5368 's PackagesSI5368 's pdf datasheet

SI5368 Pinout, Pinouts
SI5368 pinout,Pin out
This is one package pinout of SI5368,If you need more pinouts please download SI5368's pdf datasheet.

SI5368 Application circuits
SI5368 circuits
This is one application circuit of SI5368,If you need more circuits,please download SI5368's pdf datasheet.

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